HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 times the REFCLK
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D10 is transmitted first in 10-bit mode. D0 is trans-
mitted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2042 operates with either 10-bit or 20-bit par-
allel data inputs. Word width is selectable via the
DWS pin. In 10-bit mode, D10–D19 are used and
D0–D9 are ignored.
Reference Clock Input
S2042/S2043
The reference clock input (REFCLK) must be sup-
plied with a single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the
transmitted data meets the Fibre Channel frequency
limits. The internal serial clock is frequency locked to
the reference clock. The word rate clock (TCLK, TCLKN)
output frequency is determined by the selected oper-
ating speed and word width. Refer to Table 1 for
TCLK/TCLKN clock frequencies.
Table 1. Transmitter Operating Modes
Reference
TCLK/TCLKN
Clock
Word
Data Rate Width Frequency Frequency
(MHz)
(MHz)
RATESEL DWS REFSEL (Mbits/sec) (Bits)
0
0
1
1
Open
1
0
1
0
1
1
0
1
0
1
1062.5
1062.5
531.25
531.25
265.625
10
20
10
20
10
106.25
53.125
53.125
26.5625
26.5625
53.125
53.125
53.125
26.5625
26.5625
Table 2. Data Mapping to 8b/10b Alphabetic Representation
First Data Byte
TX[00:19] or
RX[00:19]
8b/10b alphabetic
representation
Second Data Byte
7
g
8
h
9
j
10
a
11 12 13
b
c
d
14 15
e
i
16
f
17
g
18 19
h
j
0
a
1
b
2
c
3
d
4
e
5
i
6
f
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Figure 4. S2043 Functional Block Diagram
LOCK_REF
RATESEL
REFCLK
REFSEL
D
LOCKDETN
SHIFT
REGISTER
RX
RY
RLX
RLY
LPEN
SYNCEN
DWS
2:1
PLL CLOCK
RECOVERY
BITCLK
D
Q
20
D(0..19)
CONTROL
LOGIC
SYNC
DETECT
LOGIC
SYNC
RCLK
RCLKN
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
3
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