DATA OUT PER SYMBOL PERIOD
DATA
Loopback Control—This bit controls the operation of
loopback. When enabled (logic 1), the rxLINE+ and rxline–
inputs are disconnected from the AFE. The rxHYB+ and
rxHYB– inputs remain connected. When disabled, the
rxLINE+ and rxLINE– inputs are connected.
BITS
Data 1
Interdata Bits
16
8
Data 1a
16
8
txBoost—This bit controls the addition of 0.5dB additional
Interdata bits
power to the output line driver.
Total Bits/Symbol Period
48
BIT
DESCRIPTION BIT STATE
OUTPUT STATE
15 (MSB) tx Enable Signal
0
1
AFE Transmits a 0 Symbol
AFE Transmits HDSL Symbol
as defined by bits 14 and 13
MSB
LSB
14
2
14 and 13
tx Symbol
Definition
00
–3 Transmit Symbol
01
11
10
–1 Transmit Symbol
+1 Transmit Symbol
+3 Transmit Symbol
Reserved
A/D Converter Data
12 - 10
rx Gain Settings
000
001
010
011
100
101
110
111
rx gain in AFE 0dB
rx gain in AFE 3dB
rx gain in AFE 6dB
FIGURE 5. Data Out Word.
rx gain in AFE 9dB
rx gain in AFE 12dB
rx gain in AFE Reserved
rx gain in AFE Reserved
rx gain in AFE Reserved
ANALOG-TO-DIGITAL CONVERTER DATA
The A/D converter data from the receive channel is coded in
twos complement.
9
8
Loopback Control
tx Boost
1
0
Loopback Mode
Normal Operation
0
1
Normal Transmit Power
+0.5dB Transmit Power Boost
ANALOG INPUT
A/D CONVERTER DATA
7 - 0
SPARE
NA
MSB
LSB
Positive Full Scale
Mid Scale
01111111111111
TABLE I. Data In.
00000000000000
10000000000000
Negative Full Scale
rxbaudCLK: This is the receive data baud rate (symbol
clock), generated by the DSP. It is 392kHz for T1 or 584kHz
for E1. It can vary from 32kHz (64kbps) to 584kHz
(1.168Mbps).
ECHO CANCELLATION IN THE AFE
The rxHYB input is subtracted from the rxLINE input for
first order echo cancellation. For correct operation, be cer-
tain that the rxLINE input is connected to the same polarity
signal at the transformer (+ to + and – to –) while the rxHYB
input is connected to opposite polarity through the compro-
mise hybrid (– to + and + to –) as shown in the Basic
Connection Diagram.
rx48xCLK: This is the A/D converter over-sampling clock,
generated by the DSP. It is 48x the receive symbol rate or
28.032MHz for 584kHz symbol rate. This clock should run
continuously.
Data Out: This is the 14-bit A/D converter output data (+2
spare bits) sent from the AFE to the DSP. The 14 bits from
the A/D Converter will be the upper bits of the 16-bit word
(bits 15-2). The spare bits (1 and 0) will be always be low.
Eight additional (interdata) bits follow which are always
high. The data is clocked out on the falling edge of rx48xCLK.
The bandwidth of the A/D converter decimation filter is
equal to one half of the symbol rate. The nominal output rate
of the A/D converter is one conversion per symbol period.
For more flexible post processing, there is a second interpo-
lated A/D conversion available in each symbol period. In
Figure 4, the first conversion is shown as Data 1 and the
second conversion is shown as Data 1a. It is suggested that
rxbaudCLK is used with the rx48xCLK to read Data 1 while
Data 1a is ignored. However, either or both outputs may be
used for more flexible post-processing.
SCALEABLE TIMING
The AFE1124 scales operation with the clock frequency. All
internal filters and the pulse former change frequency with
the clock speed so that the unit can be used at different
frequencies just by changing the clock speed.
For the receive channel, the digital filtering of the delta
sigma converter scales directly with the clock speed. The
bandwidth of the converter’s decimation filter is always one-
half of the symbol rate. The only receive channel issue in
changing baud rate is the passive single pole anti-alias filter
(see the following section). For systems implementing a
broad range of speeds, selectable cutoff frequencies for the
passive anti-alias filter should be used.
®
AFE1124
8
BB [ BURR-BROWN CORPORATION ]
