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AFE1124E 参数 Datasheet PDF下载

AFE1124E图片预览
型号: AFE1124E
PDF下载: 下载PDF文件 查看货源
内容描述: HDSL / MDSL模拟前端 [HDSL/MDSL ANALOG FRONT END]
分类和应用:
文件页数/大小: 11 页 / 162 K
品牌: BB [ BURR-BROWN CORPORATION ]
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PIN DESCRIPTIONS  
PIN #  
TYPE  
NAME  
DESCRIPTION  
1
2
3
No Connection  
No Connection  
Power  
NC  
NC  
DVDD  
Digital Supply (+3.3 to +5V)  
Digital Ground  
Transmit Baud Clock (584kHz for E1)  
Transmit Clock at 48x baud clock (28.032MHz for E1)  
Input Data Word  
Receive baud clock (584kHz for E1)  
Receive clock at 48x baud clock (28.032MHz for E1)  
Output Data Word  
Digital Supply (+3.3 to +5V)  
Digital Ground  
4
5
6
7
8
9
Ground  
Input  
Input  
Input  
Input  
Input  
Output  
Power  
Ground  
Power  
Input  
DGND  
txbaudCLK  
tx48xCLK  
Data In  
rxbaudCLK  
rx48xCLK  
Data Out  
DVDD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DGND  
AVDD  
Analog Supply (+5V)  
rxHYB–  
rxHYB+  
rxLINE–  
rxLINE+  
AGND  
vrREFP  
VCM  
vrREFN  
AVDD  
AGND  
txLINE–  
AVDD  
txLINE+  
AGND  
NC  
Negative input from hybrid network  
Positive input from hybrid network  
Negative line input  
Positive line input  
Analog Ground  
Positive reference output  
Common-mode voltage (buffered)  
Negative reference output  
Analog Supply (+5V)  
Analog Ground  
Negative line output  
Input  
Input  
Input  
Ground  
Output  
Output  
Output  
Power  
Ground  
Output  
Power  
Output buffer supply (+5V)  
Positive line output  
Output buffer ground  
Output  
Ground  
No Connection  
BLOCK DIAGRAM  
txLINE+  
txLINE–  
Pulse  
Former  
Filter  
Output  
Buffer  
REFP  
VCM  
txbaudCLK  
tx48xCLK  
Data In  
Voltage  
Reference  
Transmit  
Control  
REFN  
rxbaudCLK  
rx48xCLK  
Data Out  
Receive  
Control  
rxLINE+  
rxLINE–  
rxHYB+  
rxHYB–  
∆Σ  
Modulator  
Decimation  
Filter  
®
AFE1124  
4