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CAT25020VI 参数 Datasheet PDF下载

CAT25020VI图片预览
型号: CAT25020VI
PDF下载: 下载PDF文件 查看货源
内容描述: 1K / 2K / 4K SPI串行EEPROM CMOS [1K/2K/4K SPI Serial CMOS EEPROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 11 页 / 75 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT25010/20/40
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25010/20/40 to interface
directly with many of today’s popular microcontrollers.
The CAT25010/20/40 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
Figure 1. Sychronous Data Timing
V
IH
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25010/20/40. During a read
cycle, data is shifted out on the falling edge of the serial
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
t
HO
t
DIS
HI-Z
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X=0 for 25010, 25020. X=A8 for 25040
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1006, Rev. L
4