CAT28F010
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V
±10%,
unless otherwise specified.
28F010-70
\JEDEC
Symbol
t
AVAV
t
AVWL
t
WLAX
t
DVWH
t
WHDX
t
ELWL
t
WHEH
t
WLWH
t
WHWL
t
WHWH1(2)
t
WHWH2(2)
t
WHGL
t
GHWL
t
VPEL
Standard
Symbol
t
WC
t
AS
t
AH
t
DS
t
DH
t
CS
t
CH
t
WP
t
WPH
-
-
-
-
-
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
CE
Setup Time
CE
Hold Time
WE
Pulse Width
WE
High Pulse Width
Program Pulse Width
Erase Pulse Width
Write Recovery Time
Before Read
Read Recovery Time
Before Write
V
PP
Setup Time to
CE
Min. Max
70
0
40
40
10
0
0
40
20
10
9.5
6
0
100
Min. Max.
90
0
40
40
10
0
0
40
20
10
9.5
6
0
100
Min. Max. Unit
120
0
40
40
10
0
0
40
20
10
9.5
6
0
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
µs
ns
28F010-90
28F010-12
ERASE AND PROGRAMMING PERFORMANCE
(1)
Parameter
Chip Erase Time
(3)(5)
Chip Program Time
(3)(4)
28F010-55
Min. Typ. Max.
0.5
2
10
12.5
28F010-70
Min. Typ. Max.
0.5
2
10
12.5
28F010-90
Min. Typ. Max
0.5
2
10
12.5
28F010-12
Min. Typ. Max. Unit
0.5
2
10
Sec
12.5 Sec
Note:
(1) Please refer to Supply characteristics for the value of V
PPH
and V
PPL
. The V
PP
supply can be either hardwired or switched. If V
PP
is
switched, V
PPL
can be ground, less than V
CC
+ 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V
PP
.
(4) Minimum byte programming time (excluding system overhead) is 16
µs
(10
µs
program + 6
µs
write recovery), while maximum is 400
µs/
byte (16
µs
x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 25005-0A 2/98 F-1
6
CATALYST [ CATALYST SEMICONDUCTOR ]
