CS4349
.
t
lrckh
LRCK
(input)
t
lckd
SCLK
(input)
t
lcks
t
sckh
t
sckl
LRCK
(Input)
t
fss
t
fsh
t
sckh
t
sckl
SCLK
(Input)
t
ds
SDIN
(input)
t
dh
MSB
MSB-1
SDIN
(Input)
t
ds
t
dh
MSB
MSB-1
Figure 6. Serial Port Timing, Non-TDM Mode
Figure 7. Serial Port Timing, TDM Mode
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C
L
= 20 pF.
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
Symbol
f
scl
t
irs
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
rc
, t
rc
t
fc
, t
fc
t
susp
t
ack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
300
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Note:
9. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
RST
t
Stop
irs
Sta rt
R e p e a te d
Sta rt
t rd
t fd
Stop
SDA
t
buf
t
hdst
t
high
t
hdst
t fc
t susp
SCL
t
t
t sud
t ack
t sust
t rc
lo w
hdd
Figure 8. Control Port Timing - I²C Format
14
DS782F1
CIRRUS [ CIRRUS LOGIC ]
