CS4349
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C
L
= 20 pF.
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Transition Time from CCLK to CDOUT Valid
Time from CS rising to CDOUT High-Z
Symbol
f
sclk
t
srs
t
spi
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
t
scdov
t
cscdo
Min
-
500
500
1.0
20
66
66
40
15
-
-
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For F
SCK
< 1 MHz.
13. CDOUT should
not
be sampled during this time.
RST
t srs
CS
t spi t css
CCLK
t r2
CDIN
t scl
t
sch
t
csh
t f2
t dsu t
dh
CDOUT
Hi-Impedance
t scdov
t scdov
t cscdo
Figure 9. Control Port Timing - SPI Mode
DS782F1
15
CIRRUS [ CIRRUS LOGIC ]
