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CS4349-CZZ 参数 Datasheet PDF下载

CS4349-CZZ图片预览
型号: CS4349-CZZ
PDF下载: 下载PDF文件 查看货源
内容描述: 192 kHz的DAC W /音量控制和1 Vrms的@ 3.3 V [192 kHz DAC w/ Volume Control and 1 Vrms @ 3.3 V]
分类和应用:
文件页数/大小: 40 页 / 819 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4349
4. APPLICATIONS
4.1
Sample Rate Range and Oversampling Mode Detect
The device operates in one of three oversampling modes based on the input sample rate. In Control Port
Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In
Stand-Alone Mode, the sample rate range will be according to
4.1.1
Sample Rate Auto-Detect
The Auto-Detect feature is enabled by default. In this state, the CS4349 will auto-detect the correct mode
when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in
Sample rates outside the specified range for each mode are not supported when Auto-Detect is
enabled.
Input Sample Rate (Fs)
30 kHz - 54 kHz
60 kHz - 108 kHz
120 kHz - 216 kHz
Table 1. CS4349 Auto-Detect
Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
In Control Port Mode, the Auto-Detect feature can be disabled by the Functional Mode (FM[1:0]) bits in
the control port register 02h. In this state, the CS4349 will not auto-detect the correct mode based on the
input sample rate (Fs). The operational mode must then be set manually according to one of the ranges
referred to in
Sample rates outside the specified range for each mode are not supported.
In Stand-Alone Mode, it is not possible to disable auto-detect of sample rates.
4.2
System Clocking
The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right
clock, defined also as the input sample rate (F
s
).
Refer to
for the required SCLK-to-LRCK timing associated with the selected digital interface for-
mat, and
for the maximum allowed clock fre-
quencies.
18
DS782F1