RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.9 DPLL Configuration
4.9 DPLL Configuration
Table 4-6. DPLL Configuration Write Registers
Address
0xD5
0xD6
0xD7
0xD8
0xDB
0xF6
Register Label
DPLL_RESID_LO
DPLL_RESID_HI
DPLL_FACTOR
DPLL_GAIN
DPLL_PINI
DPLL_RST
Bits
8
8
8
7
8
—
DPLL Residual
DPLL Residual
DPLL Factor
DPLL Gain
Name/Description
DPLL Phase Detector Init (optional for RS8953B)
DPLL Phase Detector Reset
The DPLL synthesizes the PCM Receive Clock (RCLK) output from the 60 through 80 MHz Reference Clock
(HFCLK) generated internally by PLL multiplication of MCLK, or input directly on MCLK [see PLL_MUL
and PLL_DIS in CMD_1; addr 0xE5]. HFCLK must operate in the 60 to 80 MHz frequency range, but requires
no specific phase or frequency relationship to the PCM or HDSL channels. The nominal frequency (f
PCM
) of
RCLK is synthesized by setting the DPLL_FACTOR and DPLL_RESID values according to the integer and
fractional results of the following formula:
f
MCLK
×
PLL_MUL
-
[INTEGER.FRACTION] =
------------------------------------------------
2
×
f
PCM
where:
f
MCLK
f
PCM
INTEGER
FRACTION
PLL_MUL
PLL_DIV
= MCLK input frequency
= RCLK output frequency desired
= Integer part of result [DPLL_FACTOR; addr 0xD7]
= Fractional part of result [DPLL_RESID; addr 0xD5]
= PLL multiplication factor [CMD_1; addr 0xE5]
= PLL scale factor [CMD_1; addr 0xE5]
The DPLL phase detector operates from the 10–15 MHz General Purpose Clock (GCLK) which equals
HFCLK divided by PLL scale factor:
f
MCLK
×
PLL_MUL
GCLK =
-------------------------------------------------
PLL_DIV
0xD5—DPLL Residual (DPLL_RESID_LO)
7
6
5
4
3
2
1
0
DPLL_RESID[7:0]
N8953BDSB
Conexant
4-35
CONEXANT [ CONEXANT SYSTEMS, INC ]
