4.0 Registers
4.9 DPLL Configuration
RS8953B/8953SPB
HDSL Channel Unit
0xD6—DPLL Residual (DPLL_RESID_HI)
7
6
5
4
3
2
1
0
DPLL_RESID[15:8]
DPLL_RESID[15:0]
DPLL Residual—Works in conjunction with DPLL_FACTOR to define the DPLL nominal
free-running frequency in Open Loop Mode or the DPLL initial frequency in Closed Loop
Mode [DPLL_NCO in CMD_5; addr 0xE9]. The DPLL_RESID value is sampled by the
DPLL only after the MPU writes RX_RST [address 0xF1], or after the master HDSL channel’s
receive framer transitions to an IN_SYNC state.
DPLL_RESID =
round
(
FRACTION
×
65535
)
DPLL_FACTOR = 257 – INTEGER
where:
round ( )
= Round to nearest integer
FRACTION = Fraction from INTEGER.FRACTION calculation
INTEGER
= Integer from INTEGER.FRACTION calculation
Assuming MCLK operates at eight times the BCLKn frequency (16 times symbol rate) and RCLK is desired
to operate at standard T1 or E1 clock rates. The following examples show HTU application values for
DPLL_RESID and DPLL_FACTOR:
HTU
2T1
3E1
2E1
PLL_MUL
11
11
8
PLL_DIV
6
6
6
DPLL_FACTOR
0xEB
0xF1
0xEF
DPLL_RESID
0x578B
0xD7FF
0x4000
0xD7—DPLL Factor (DPLL_FACTOR)
7
6
5
4
3
2
1
0
DPLL_FACTOR[7:0]
DPLL_FACTOR[7:0]
DPLL Factor—Works in conjunction with DPLL_RESID.
4-36
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
