RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.9 DPLL Configuration
0xD8—DPLL Gain (DPLL_GAIN)
7
—
6
5
DC_GAIN[2:0]
4
3
2
DC_INTEG[3:0]
1
0
DPLL_GAIN[7:0]
DPLL Gain—Filtering is controlled by two DC parameters: DC_GAIN, which represents
proportional loop gain, and DC_INTEG, which represents the filter’s integration coefficient.
The DPLL closed loop bandwidth is programmed to be in the range of 0.2 Hz to 3 Hz. The
following approximations are used to calculate DC parameters for a desired DPLL bandwidth:
BW
DC_GAIN = --------------------
×
2
17
N
×
26.5
(
BW
)
2
2
15
-
-
DC_INTEG = ---------------
×
-------
N
26.5
2
where:
N
= RCLK output frequency
÷
64000
BW
= DPLL closed loop bandwidth (in Hz)
Specific DC parameter values are programmed according to the following tables:
DC_GAIN[2:0]
000
001
010
011
100
101
110
111
DC_INTEG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010–1110
1111
RS8953B
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
RS8953B
2
–4
2
–3
2
–2
2
–1
1
2
1
2
2
2
3
2
4
2
5
2
6
0 (Type I)
N8953BDSB
Conexant
4-37
CONEXANT [ CONEXANT SYSTEMS, INC ]
