CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device.
demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
RESET (RS)
DATA IN (D)
18
Write
Write
Write
9
9
RESET (RS)
Read CLOCK (RCLK)
Read ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EF EMPTY FLAG (EF) #2
FF
9
9
CLOCK (WCLK)
ENABLE 1 (WEN1)
ENABLE 2/LOAD
(WEN2/LD)
CY7C42X1
CY7C42X1
PROGRAMMABLE (PAF)
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
FF
EF
DATA OUT (Q)
18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory
Used in a Width Expansion Configuration
Document #: 38-06016 Rev. *C
Page 6 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
