CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
(continued)
Reset Timing
t
RS
t
RSS
REN1,
REN2
t
RSS
WEN1
t
RSS
WEN2/LD
RS
t
RSR
t
RSR
t
RSR
t
RSF
EF,PAE
t
RSF
FF,PAF,
t
RSF
Q
0 -
Q
8
OE = 1
OE = 0
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D
0
–D
8
t
ENS
D
0
(FIRST
VALID
Write)
D
1
D
2
D
3
D
4
WEN1
WEN2
(if applicable)
t
SKEW1
t
FRL
RCLK
t
REF
EF
REN1,
REN2
Q
0
–Q
8
t
OLZ
t
OE
t
A
t
A
D
0
D
1
OE
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
19. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
20. When t
SKEW1
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW1
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or
t
CLK
+ t
SKEW1
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
21. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *C
Page 10 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
