CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
Write Cycle Timing
t
CLK
t
CLKH
WCLK
t
CLKL
t
DS
D
0
–D
8
t
ENS
WEN1
t
DH
t
ENH
NO OPERATION
WEN2
(if applicable)
FF
t
SKEW1
RCLK
NO OPERATION
t
WFF
t
WFF
REN1,REN2
Read Cycle Timing
t
CKL
t
CLKH
RCLK
t
ENS
REN1,REN2
t
REF
EF
t
A
Q
0
–Q
8
t
OLZ
OE
t
OE
t
ENH
t
CLKL
NO OPERATION
t
REF
VALID DATA
t
OHZ
t
SKEW1
WCLK
WEN1
WEN2
Notes:
15. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK rising edge.
16. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *C
Page 9 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
