DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Figure 1. Block Diagram
Table 1. Operating Modes
V
CC
CE
V
IH
V
CC
> V
PF
V
IL
V
IL
V
IL
V
SO
< V
CC
<V
PF
<V
BAT
X
X
OE
X
X
V
IL
V
IH
X
X
WE
X
V
IL
V
IH
V
IH
X
X
DQ0–DQ7
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1553 is in read mode whenever
CE
(chip enable) is low and
WE
(write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within t
AA
after the last address input is stable, provided that
CE
and
OE
access times are satisfied. If
CE
or
OE
access times are not met, valid data is available at the latter of
chip-enable access (t
CEA
) or at output-enable access time (t
OEA
). The state of the DQ pins is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data lines are driven to an intermediate state until
t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data remains valid for
output data hold time (t
OH
) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
and
WE
must return inactive for a minimum of t
WR
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for t
DH
afterward. In a typical application, the
OE
signal is high during a write cycle. However,
OE
can be active
provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
3 of 19
DALLAS [ DALLAS SEMICONDUCTOR ]
