DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Table 3. Alarm Mask Bits
AM4
1
1
1
1
0
AM3
1
1
1
0
0
AM2
1
1
0
0
0
AM1
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
When the RTC register values match Alarm register settings, the Alarm Flag bit (AF) is set to 1. If the
Alarm Flag Enable (AE) is also set to 1, the alarm condition activates the
IRQ
/FT pin. The
IRQ
/FT signal
is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figures 2 and 3. When
CE
is active, the
IRQ
/FT signal may be cleared by having the address stable for as short as 15ns and either
OE
or
WE
active, but it is not guaranteed to be cleared unless t
RC
is fulfilled. The alarm flag is also
cleared by a read or write to the Flags register, but the flag does not change states until the end of the
read/write cycle and the
IRQ
/FT signal has been cleared.
Figure 2. Clearing
IRQ
Waveforms
CE
,
0V
Figure 3. Clearing
IRQ
Waveforms
CE = Ø
The
IRQ
/FT pin can also be activated in the battery-backed mode. The
IRQ
/FT goes low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however, an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery-backup mode and power-up states.
7 of 19
DALLAS [ DALLAS SEMICONDUCTOR ]
