DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
was issued. Normal updates to the external set of registers resume within 1 second after the read bit is set
to 0 for a minimum of 500ms. The read bit must be 0 for a minimum of 500ms to ensure the external
registers are updated.
SETTING THE CLOCK
The 8th bit, B7 of the Control register, is the write bit. Setting the write bit to 1, like the read bit, halts
updates to the DS1553 (1FF8h–1FFFh) registers. After setting the write bit to 1, RTC registers can be
loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0
then transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1553 is guaranteed to keep time accuracy to within
±1
minute per month at +25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy and caution should be taken to place the
RTC in the lowest level EMI section of the PC board layout. For additional information, refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks
on our website at
CLOCK ACCURACY (PowerCap MODULE)
The DS1553 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within
±1.53
minutes per month (35ppm) at +25°C. The
electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest
level EMI section of the PC board layout. For additional information, refer to
Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks
on our website at
FREQUENCY TEST MODE
The DS1553 frequency test mode uses the open-drain
IRQ
/FT output. With the oscillator running, the
IRQ
/FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the
Watchdog Steering bit (WDS) is 1 or the Watchdog register is reset (Register 1FF7h = 00h). The
IRQ
/FT
output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz
RTC oscillator. The
IRQ
/FT pin is an open-drain output that requires a pullup resistor for proper
operation. The FT bit is cleared to 0 on power-up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1553 reside within registers 1FF2h–1FF5h. Register 1FF6h
contains two alarm-enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the
IRQ
/FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1553 is in the battery-backed state of
operation to serve as a system wakeup. Alarm mask bits AM1–AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.
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DALLAS [ DALLAS SEMICONDUCTOR ]
