EDS2516APTA
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-60
Parameter
System clock cycle time
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low
impedance
CLK to Data-out high
impedance
Input setup time
Input hold time
Symbol
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
tHI
min.
6
2.5
2.5
—
2.5
1
—
1.5
1
60
42
18
18
max.
—
—
—
5.0
—
—
5.0
—
—
—
120000
—
—
—
—
—
5
-7A
min.
7.5
2.5
2.5
—
3.0
1
—
1.5
0.8
60
45
15
15
15
2CLK +
15ns
15
0.5
max.
—
—
—
5.4
—
—
5.4
—
—
—
120000
—
—
—
—
—
5
-75
min.
7.5
2.5
2.5
—
3.0
1
—
1.5
0.8
67.5
45
20
20
15
2CLK +
20ns
15
0.5
—
max.
—
—
—
5.4
—
—
5.4
—
—
—
120000
—
—
—
—
—
5
ns
ns
ms
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
EO
Ref/Active to Ref/Active
command period
Active to Precharge
command period
Active command to column
command (same bank)
Precharge to active
command period
Write recovery or data-in to
precharge lead time
Last data into active
latency
Active (a) to Active (b)
command period
Transition time (rise and
fall)
Refresh period
(8192 refresh cycles)
tRC
tRAS
tRCD
tRP
L
tDPL
12
tDAL
tRRD
tT
tREF
12
0.5
—
2CLK +
18ns
od
Pr
64
—
64
64
Notes: 1.
2.
3.
4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
Access time is measured at 1.4V. Load condition is CL = 50pF.(in case of -60, CL = 30pF)
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
t
uc
Data Sheet E0359E20 (Ver. 2.0)
7
ELPIDA [ ELPIDA MEMORY ]
