EDS2516APTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Symbol
ICC1
ICC2P
ICC2PS
Grade
-60, -7A
-75
max.
135
115
3
2
20
9
4
3
30
15
-60
-7A, -75
-60, -7A
-75
180
145
250
220
3
-XXL
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Standby current in non power down ICC2N
Standby current in non power down
(input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
power down (input signal stable)
Burst operating current
Refresh current
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
EO
Self refresh current
Self refresh current
(L-version)
Data Sheet E0359E20 (Ver. 2.0)
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
L
ICC6
ICC6
od
Pr
5
t
uc
ELPIDA [ ELPIDA MEMORY ]
