EDS2516APTA
Test Conditions
•
Input and output timing reference levels: 1.4V
•
Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V
0.8 V
I/O
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-60
166
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
6.0
3
10
7
3
2
2
1
-7A
133
7.5
2
8
6
2
2
2
1
-75
133
7.5
3
9
6
3
2
2
1
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Notes
1
1
1
1
1
1
2
= [lDPL +
lRP]
= [lRC]
3
EO
Frequency (MHz)
tCK (ns)
Self refresh exit time
(CL = 3)
(CL = 3)
DQM to data in
DQM to data out
CKE to CLK disable
/CS to command disable
Data Sheet E0359E20 (Ver. 2.0)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
Precharge command to high impedance
(CL = 2)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early
precharge)
(CL = 2)
Column command to column command
Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1.
lRCD
to
lRRD
are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
L
od
Pr
5
4
5
tCK
lSEC
lHZP
lHZP
10
8
9
tCK
tCK
—
2
2
3
3
3
tCK
lAPR
1
1
1
tCK
lEP
—
–1
–1
tCK
lEP
–2
1
–2
1
–2
1
tCK
lCCD
tCK
lWCD
lDID
lDOD
lCLE
lMRD
lCDD
lPEC
0
0
0
tCK
0
2
1
2
0
1
0
2
1
2
0
1
0
2
1
2
0
1
tCK
tCK
tCK
tCK
tCK
tCK
t
uc
8
ELPIDA [ ELPIDA MEMORY ]
