HM534253BJ-8 参数 Datasheet PDF下载

HM534253B Series

SAM Column Decoder

DR1

SAM I/O Bus

AX8 = 0

SAM I/O Bus

Memory

Array

DR3

DR0

SAM I/O Buffer

SI/O

Figure 5 Block Diagram for Split Transfer

DR2

EO

Split read transfer cycle is set when

CAS

is high,

DT/OE

is low,

WE

is high and DSF is high at the falling

edge of

RAS.

The cycle can be executed asyncronously with SC. However, t

STS

(min) timing specified

between SC rising and

RAS

falling must be satisfied. SAM last address must be accessed, satisfying t

RST

(min), t

CST

(min), and t

AST

(min) timings specified between

RAS

or

CAS

falling and column address. (See

figure 6.)

In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch

SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle.

LP

Memory

Array

AX8 = 1

Data Sheet E0165H10

13

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