HM534253B Series
Serial Write Cycle
If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode.
In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is
high, SI/O data isn’t fetched into data register. Internal pointer is incremented by the SC rising, so SE high
can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer
indicates address 0 at the next access.
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2)
CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate
RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is
required when all row addresses are accessed within 8 ms.
(1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only RAS cycle with CAS
fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this
cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS.
(2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh
address need not to be input through external circuits because it is input through an internal refresh
counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits
don’t operate.
(3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating
RAS when DT/OE and CAS keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–0.5 to +7.0
50
1
1
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Note: 1. Relative to VSS.
Data Sheet E0165H10
15
ELPIDA [ ELPIDA MEMORY ]
