HM534253B Series
RAS
tSTS (min)
tRST (min)
CAS
tCST(min)
Yj
Address
Xi
tAST(min)
DT/OE
DSF
255
(511)
n
(n + 255)
511
SC
255 + Yj
(Yj)
(255)
Figure 6 Limitation in Split Transfer
Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF high at the falling edge of RAS)
A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write
transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), t (min), tCST (min) and tAST
RST
(min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state
in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into input
state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other
addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed before split
write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that of the read
transfer cycle or the split read transfer cycle.
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address
511), the internal pointer indicates address 0 at the next access.
Data Sheet E0165H10
14
ELPIDA [ ELPIDA MEMORY ]
