EM6320FP16AS-70L 参数 Datasheet PDF下载

merging Memory & Logic Solutions Inc.

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1).

EM610FV8T Series

Low Power, 128Kx8 SRAM

(Address Controlled, CS1=OE=V

IL

, CS2= WE=V

IH

)

t

RC

Address

t

AA

t

OH

Data Out

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2)

(WE = V

IH

)

t

RC

Address

t

AA

CS1

t

C O

t

OH

CS2

t

HZ

t

OE

OE

t

OLZ

Data Out

High-Z

Data Valid

t

OHZ

t

LZ

NOTES (READ CYCLE)

1. t

HZ

and t

OHZ

are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.

2. At any given temperature and voltage condition, t

HZ

(Max.) is less than t

LZ

(Min.) both for a given device and from device to device

interconnection.

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