merging Memory & Logic Solutions Inc.
TIMING WAVEFORM OF WRITE CYCLE(3) ( CS
2
CONTROLLED)
EM610FV8T Series
Low Power, 128Kx8 SRAM
t
WC
Address
t
CW
(2)
CS1
t
AS
(3)
t
W R
(4)
CS2
t
AW
t
W P
(1)
WE
t
DW
Data in
Data out
High-Z
Data Valid
t
DH
High-Z
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS
1
, a high CS
2
and low WE. A write begins at the latest
transition among CS
1
goes low, CS
2
goes high and WE goes low. A write ends at the earliest transition
when CS
1
goes high, CS
2
goes hagh and WE goes high. The t
WP
is measured from the beginning of write
to the end of write.
2. t
CW
is measured from the CS
1
going low to end of write.
3. t
A S
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as CS
1
or WE
going high.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
