EM6603
1
Operating modes
Figure 4.Mode Transition diagram
The EM6603 has two low power dissipation modes:
STANDBY and SLEEP. Figure 4 is a transition
diagram for these modes.
1.1
STANDBY Mode
Executing a HALT instruction puts the EM6603 into
STANDBY mode. The voltage regulator, oscillator,
Watchdog timer, interrupts and timer/event counter are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers, RAM,
and I/O pins retain their states prior to STANDBY
mode. STANDBY is cancelled by a RESET or an
Interrupt request if enabled.
Table 2
:
shows the state of the EM6603 functions in
Table 2.StandBy and Sleep Activities
FUNCTION
STANDBY SLEEP
Oscillator
Active
Stopped
Instruction Execution Stopped
Stopped
Registers and Flags Retained
Reset
Interrupt Functions
Active
Stopped
RAM
Retained
Retained
Timer/Counter
Active
Stopped
Watchdog
Active
Stopped
I/O pins
Active
High-Z or
Retained
Supply VLD
Stopped
Stopped
Reset pin
Active
Active
1.2
SLEEP MODE
Writing to the
SLEEP*
bit in the
IntRq*
register puts
the EM6603 in SLEEP mode. The oscillator stops and
most functions of the EM6603 are inactive. To be able
to write the
SLEEP
bit, the
SLmask
bit must first be
set to 1. In SLEEP mode only the voltage regulator
and RESET input are active. The RAM data integrity is
maintained. SLEEP mode may be cancelled only by a
RESET at the terminal pin of the EM6603. The RESET
must be high for at least 2µsec.
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to
guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe output
STB/RST is high. Waking up from SLEEP mode clears the
SLEEP
flag but not the
SLmask
bit. By reading
SLmask
one can therefore determine if the EM6603 was powered up (SLmask = 0), or woken from SLEEP mode
(SLmask = 1).
2
Power Supply
The EM6603 is supplied by a single external power supply between Vdd and Vss, the circuit reference being at
Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and internal
logic. Output drivers are supplied directly from the external supply Vdd. A typical connection configuration is shown
in Figure 3.
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration shown in Fig.3 should be used.
*registers are marked in bold and underlined like
*Bits/Flags
in registers are marked in bold only like
Copyright
2002, EM Microelectronic-Marin SA
IntRq
SLEEP
03/02 REV. G/439
5
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