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M53D128168A_1 参数 Datasheet PDF下载

M53D128168A_1图片预览
型号: M53D128168A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行移动DDR SDRAM [2M x 16 Bit x 4 Banks Mobile DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 46 页 / 1076 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted,T
A
= -40 to 85 °C
Parameter
Operating Current
(One Bank Active)
Symbol
I
CC0
I
CC2P
Precharge Standby
Current in power-down
mode
Test Condition
M53D128168A
Operation Temperature Condition -40°C~85°C
Version
-7.5
60
-10
50
Unit
mA
mA
t
RC
= t
RC
(min), t
CK
= t
CK
(min), CKE = High,
/CS = High between valid commands, address
inputs are switching, data input signals are stable
All banks idle,
CKE = Low, /CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
All banks idle,
CKE = Low, /CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
All banks idle,
CKE = Low, /CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
All banks idle,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
CKE = Low, CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
One bank active,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
CKE = Low, CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
One bank active,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
BL=4, t
CK
= t
CK
(min), continuous read bursts,
I
OUT
= 0 mA, address inputs are switching, 50%
data changing each burst
One bank active,
BL=4, t
CK
= t
CK
(min), continuous write bursts,
I
OUT
= 0 mA, address inputs are switching, 50%
data changing each burst
Burst refresh,
t
RC
= t
RC
(min), t
CK
= t
CK
(min), CKE = High,
address inputs are switching, data input signals
are stable
0.5
I
CC2PS
0.5
mA
Precharge Standby
Current in non
power-down mode
I
CC2N
28
22
mA
I
CC2NS
28
22
mA
I
CC3P
Active Standby Current
in power-down mode
I
CC3PS
5
mA
2
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3N
45
35
mA
I
CC3NS
25
20
mA
Operating Current
(Burst Mode)
I
CC4R
90
75
mA
I
CC4W
90
75
mA
Refresh Current
I
CC5
75
60
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
4/46