Etr onTech
(V
DD
= 3.3
±
0.3 V, Ta = 0~70
°C)
Symbol
Parameter
4Mx16 DDR SDRAM
EM658160
Electrical Characteristics and Recommended A.C. Operating Conditions
- 3.3/3.5/4/5/6/7/8
Min.
Max.
Unit
t
RC
t
RFC
t
RAS
t
RCD
t
RP
t
RRD
tw
R
t
CDLR
t
CCD
t
CK
Row cycle time
Refresh row cycle time
Row active time
/RAS to /CAS Delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. Address to Col. Address delay
44/44/44/55/60/70/80
56/56/56/70/84/91/96
32/32/32/40/42/49/56
12/12/12/15/18/21/24
12/12/12/15/18/21/24
6.6/7/8/10/12/14/16
2
2.5t
CK-
t
DQSS
1
3.3/3.5/4/5/6/7/8
5/5/5.5/6/7.5/8/9
6/6/7/8/9/10/11
0.45
0.45
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8
-0.5/-0.5/-0.5/-0.5/-0.5/-0.5/-0.6
0.9
0.4
0.75
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.4
0.4
0.4
1.1
1.1
1
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.3
t
IS
+1t
CK
12/12/11/11/10/10/10
200
t
IS
+2t
CK
0.6
0.6
0.6
15
15
15
0.55
0.55
0.6/0.6/0.6/0.7/0.7/0.75/0.8
0.6/0.6/0.6/0.7/0.7/0.75/0.8
0.5/0.5/0.5/0.5/0.5/0.5/0.6
1.1
0.6
1.25
120000
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
ns
Clock cycle time
CL*=3
CL*=2.5
CL*=2
t
CH
t
CL
Clock high level width
Clock low level width
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
t
CK
ns
ns
t
CK
t
CK
t
CK
ns
ns
t
CK
ns
ns
t
CK
ns
t
CK
t
CK
t
DQSCK
DQS-out access time from CK,/CK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
Output access time from CK,/CK
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
t
WPRES
DQS-in setup time
t
WPREH
DQS-in hold time
t
WPST
t
DQSH
t
DQSL
t
IS
t
IH
t
MRD
t
DS
t
DH
t
QH
t
PDEX
t
XSA
t
XSR
DQS write postamble
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Output DQS valid window
Power down exit time
Self refresh exit to active
command delay
Self refresh exit to read
command delay
Etron Confidential
10
Rev. 1.1
Jan. 2002