Et r on Tech
EM658160
4Mx16 DDR SDRAM
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS
.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK
4. Power-up sequence is described in Note 6.
5. A.C. Test Conditions
.
SSTL_2 Interface
Reference Level of Output Signals (VRFE
Output Load
)
0.5 * V
DDQ
Reference to the Under Output Load (A)
VREF+0.35 V / VREF-0.35 V
1 V/ns
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 * V
DDQ
0.5*VDDQ
Ω
25
Ω
25
Output
30pF
SSTL_2 A.C. Test Load
6. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and
maintain CKE “LOW”. Power applied to VDDQ the same time as VTT and VREF.
2) After power-up, No-Operation of 200 µ−seconds minimum is required.
3) Start clock and keep CKE “HIGH” to maintain either No-Operation or Device Deselect at the input.
4) Issue EMRS – enable DLL.
5) Issue MRS – reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are
needed for DLL lock)
6) Precharge all banks of the device.
7) Two or more Auto Refresh commands.
8) Issue MRS – Initialize device operation.
Etron Confidential
11
Rev. 1.1
Jan. 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
