欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM658160TS-8 参数 Datasheet PDF下载

EM658160TS-8图片预览
型号: EM658160TS-8
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×16的DDR同步DRAM (SDRAM)的 [4M x 16 DDR Synchronous DRAM (SDRAM)]
分类和应用: 内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 26 页 / 158 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
 浏览型号EM658160TS-8的Datasheet PDF文件第1页浏览型号EM658160TS-8的Datasheet PDF文件第2页浏览型号EM658160TS-8的Datasheet PDF文件第3页浏览型号EM658160TS-8的Datasheet PDF文件第4页浏览型号EM658160TS-8的Datasheet PDF文件第6页浏览型号EM658160TS-8的Datasheet PDF文件第7页浏览型号EM658160TS-8的Datasheet PDF文件第8页浏览型号EM658160TS-8的Datasheet PDF文件第9页  
Etr onTech
Operation Mode
4Mx16 DDR SDRAM
EM658160
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Extended MRS
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
DM BS
0,1
A
10
A
0-9,11
/CS /RAS /CAS /WE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
Row address
L
H
L
H
L
H
X
X
Column
address
(A0 ~ A7)
Column
address
(A0 ~ A7)
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
H
H
H
L
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
OP code
OP code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
L
L
H
L
X
H
L
X
H
L
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(5)
Active
Any
(PowerDown)
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
X
H
X
X
X
X
X
Note:
1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Etron Confidential
5
Rev. 1.1
Jan. 2002