Freescale Semiconductor, Inc.
System Integration Module (SIM)
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 9-5. Internal Reset Timing
Freescale Semiconductor, Inc...
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 9-6. Sources of Internal Reset
9.4.2.1 Power-On Reset (POR)
When power is first applied to the MCU, the POR generates a pulse to
indicate that power-on has occurred. The external reset pin (RST) is held
low while the SIM counter counts out 4096 CGMXCLK cycles. Another
64 CGMXCLK cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, these events occur:
•
•
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for
4096 CGMXCLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
Technical Data
System Integration Module (SIM)
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MC68HC908AS60 — Rev. 1.0
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
