Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Bus Clock Control and Generation
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
This clock can come
from either an external oscillator or from the on-chip phase-locked loop
(PLL). See
9.3.1 Bus Timing
Freescale Semiconductor, Inc...
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
9.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
OSC1
CLOCK
SELECT
CIRCUIT
CGMXCLK
SIM COUNTER
CGMVCLK
÷
2
A
CGMOUT
B S*
*When S = 1,
CGMOUT = B
÷
2
BUS CLOCK
GENERATORS
PLL
BCS
PTC3
MONITOR MODE
USER MODE
SIM
CGM
Figure 9-3. CGM Clock Signals
MC68HC908AS60 — Rev. 1.0
System Integration Module (SIM)
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Technical Data
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
