Freescale Semiconductor, Inc.
System Integration Module (SIM)
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the configuration
register (CONFIG-1). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 9-15 shows stop mode entry timing.
CPUSTOP
IAB
IDB
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
Note: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 9-15. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP –1
SP – 2
SP – 3
STOP +1
Figure 9-16. Stop Mode Recovery from Interrupt or Break
Technical Data
MC68HC908AS60 — Rev. 1.0
System Integration Module (SIM)
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