Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Registers
9.8 SIM Registers
The SIM has three memory mapped registers:
• Break status register, SBSR
• Reset status register, SRSR
• Break flag control register, SBFCR
9.8.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
SBSW
See Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
R
= Reserved
Note: Writing a logic 0 clears SBSW.
Figure 9-17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
code given here is an example of this. Writing 0 to the SBSW bit
clears it.
MC68HC908AS60 — Rev. 1.0
Technical Data
System Integration Module (SIM)
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