GS74117AX-12 参数 Datasheet PDF下载

GS74117AX

Block Diagram

A

0

Address

Input

Buffer

Row

Decoder

Memory Array

A

17

CE

WE

Control

OE

UB

_____

LB

_____

Column

Decoder

I/O Buffer

DQ

1

DQ

16

Truth Table

CE

H

OE

X

WE

X

LB

X

L

UB

X

L

H

L

L

H

L

X

H

DQ

1

to DQ

8

Not Selected

Read

Read

High Z

Write

Write

Not Write, High Z

High Z

High Z

DQ

9

to DQ

16

Not Selected

Read

High Z

Read

Write

Not Write, High Z

Write

High Z

High Z

V

DD

Current

ISB

1

, ISB

2

L

L

H

L

H

L

L

X

L

L

H

I

DD

L

L

H

X

H

X

X

H

Note: X: “H” or “L”

Rev: 1.02 10/2002

2/12

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.