11
512Mbit (16Mx32bit) Mobile SDR Memory
H55S5122DFR Series / H55S5132DFR Series
FEATURES
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Standard SDRAM Protocol
Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
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Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V
LVCMOS compatible I/O Interface
Low Voltage interface to reduce I/O power
Programmable burst length: 1, 2, 4, 8 or full page
Programmable Burst Type: sequential or interleaved
Programmable CAS latency of 3 or 2
Programmable Drive Strength
Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
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Operation Temperature
- Mobile Temp.: -30
o
C
~ 85
o
C
Package Type: 90ball FBGA, 0.8mm pitch, 8 x 13 [mm
2
], t=1.0mm max, Lead & Halogen Free
512M SDRAM ORDERING INFORMATION
Part Number
H55S5122DFR-60M
H55S5122DFR-75M
H55S5122DFR-A3M
H55S5132DFR-60M
H55S5132DFR-75M
H55S5132DFR-A3M
Clock Frequency
166MHz
133MHz
105MHz
4banks x 4Mb x 32
166MHz
133MHz
105MHz
1KBytes
(Reduced)
LVCMOS
2KBytes
(Normal)
90 Ball FBGA
Lead & Halogen
Free
Page
Size
Organization
Interface
Package
Rev 1.5 / Jan. 2009
5
HYNIX [ HYNIX SEMICONDUCTOR ]
