HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
1M
x32 Bank 3
Row
Pre
Decoder
1M x32 Bank 2
X decoder
X decoder
X decoder
X decoder
X decoder
X decoder
X decoder
1M x32 Bank 1
1M x32 Bank 0
DQ0
DQ1
I/O Buffer & Logic
I/O Buffer & Logic
Sense AMP & I/O Gate
State Machine
State Machine
Column
Active
X decoder
Memory
Cell
Array
Column
Pre
Decoder
DQ30
DQ31
Y decoder
Bank Select
Column Add
Counter
A0
A1
Address buffers
Address buffers
Address
Register
Burst
Counter
A11
BA0
BA1
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.9 / July 2004
5
HYNIX [ HYNIX SEMICONDUCTOR ]
