Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Type
Power
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
GND
CLK_EN
3
4
5
6
7
8, 9
10
11, 12
13, 18
14, 15
16, 17
19, 20
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
V
DD
nQ3, Q3
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Output
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
Pullup
high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1
Pulldown inputs. When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Inver ting differential clock input.
No connect.
Core supply pin.
Differential output pair. LVHSTL interface levels.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Pulldown Non-inver ting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
8523AGI-03
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 5, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
