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ICS9DB202CGLF 参数 Datasheet PDF下载

ICS9DB202CGLF图片预览
型号: ICS9DB202CGLF
PDF下载: 下载PDF文件 查看货源
内容描述: 两个0.7V电流模式差分HCSL输出对, 1差分时钟输入 [Two 0.7V current mode differential HCSL output pairs, 1 differential clock input]
分类和应用: 逻辑集成电路光电二极管驱动时钟
文件页数/大小: 11 页 / 263 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS9DB202  
Integrated  
Circuit  
Systems, Inc.  
PCI EXPRESS  
JITTER  
ATTENUATOR  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
PLL_BW  
CLK  
Type  
Pullup  
Description  
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.  
1
2
Input  
Input  
Pulldown Non-inverting differential clock input.  
Pullup/  
3
nCLK  
Input  
Inverting differential clock input. VDD/2 default when left floating.  
Pulldown  
4
FS0  
VDD  
Input  
Power  
Power  
Pullup Frequency select pin. LVCMOS/LVTTL interface levels.  
Core supply pins.  
5, 9, 12, 16  
6, 15  
GND  
Power supply ground.  
PCIEXT0,  
PCIEXC0  
7, 8  
Output  
Input  
Differential output pairs. HCSL interface levels.  
Output enable. When HIGH, forces outputs to HiZ state.  
Pulldown  
10, 11  
nOE0, nOE1  
When LOW, enables outputs. LVCMOS/LVTTL interface levels.  
PCIEXC1,  
PCIEXT1  
13, 14  
17  
Output  
Input  
Differential output pairs. HCSL interface levels.  
FS1  
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.  
A fixed precision resistor (475) from this pin to ground provides a  
reference current used for differential current-mode PCIEX clock outputs.  
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.  
18  
IREF  
Input  
19  
20  
BYPASS  
VDDA  
Power Pulldown  
Power  
LVCMOS/LVTTL interface levels.  
Analog supply pin. Requires 24series resistor.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical  
Maximum Units  
Input Capacitance  
Input Pullup Resistor  
4
pF  
K  
KΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO  
INPUT FREQUENCY FUNCTION TABLE, FS1  
TABLE 3C. BYPASS TABLE  
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO  
INPUT FREQUENCY FUNCTION TABLE, FS0  
Inputs  
Mode  
Inputs  
Outputs  
PCIEX0  
5/4  
Inputs  
Outputs  
PCIEX1  
1
BYPASS  
FS0  
0
FS1  
0
0
PLL Mode  
Bypass Mode  
(output = inputs)  
1
1
1
1
5/4  
TABLE 3D. OUTPUT ENABLE  
FUNCTION TABLE, NOE0  
TABLE 3E. OUTPUT ENABLE  
FUNCTION TABLE, NOE1  
TABLE 3F. PLL BANDWIDTH TABLE  
Inputs  
Outputs  
PCIEX0  
Enabled  
HiZ  
Inputs  
Inputs  
Outputs  
PCIEX1  
Enabled  
HiZ  
Bandwidth  
PLL_BW  
nOE0  
nOE1  
0
1
0
1
500kHz  
1MHz  
0
1
9DB202CG  
www.icst.com/products/hiperclocks.html  
REV. A OCTOBER 6, 2004  
2