IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 3)
t
RC
ADDRESS
t
AA
tOH
OE
CS
(5)
tOE
tOHZ
(5)
tOLZ
(5)
t
ACS
t
CHZ
(5)
t
CLZ
DATA
VALID
DATA OUT
tPU
ICC
V
CC
Supply
Currents
I
SB
t
PD
3089 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATA VALID
DATA OUT
PREVIOUS DATA VALID
3089 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3 (1, 3, 4)
CS
(5)
tACS
tCHZ
(5)
tCLZ
DATA OUT
DATA VALID
3089 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±500mV from steady state.
5.1
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
