IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1, 2, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
CONTROLLED TIMING)
WE
tWC
ADDRESS
CS
tAW
(3)
WR
(7)
tAS
tWP
t
(6)
t
CHZ
WE
DATA OUT
DATA IN
(6)
WHZ
t
(6)
t
OW
DATA (4)
VALID
(4)
PREVIOUS DATA VALID
t
DW
t
DH
DATA VALID
3089 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CONTROLLED TIMING) (1, 2, 3, 5, 7)
CS
t
WC
ADDRESS
CS
tAW
(3)
tWR
t
AS
tCW
WE
tDW
tDH
DATA IN
DATA VALID
3089 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the
I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not
apply and the write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
5.1
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
