IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table
(1, 2)
Operation
Read
Read
Write all Bytes
Write all Bytes
Write Byte 1
(3)
Write Byte 2
(3)
Write Byte 3
(3)
Write Byte 4
(3)
GW
H
H
L
H
H
H
H
H
BWE
H
L
X
L
L
L
L
L
BW
1
X
H
X
L
L
H
H
H
BW
2
X
H
X
L
H
L
H
H
BW
3
X
H
X
L
H
H
L
H
BW
4
X
H
X
L
H
H
H
L
5279 tbl 12
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2.
BW
3
and
BW
4
are not applicable for the IDT71V3578.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table
(1)
Operation
(2)
Read
Read
Write
Deselected
Sleep Mode
OE
L
H
X
X
X
ZZ
L
L
L
L
H
I/O Status
Data Out
High-Z
High-Z – Data In
High-Z
High-Z
Power
Active
Active
Active
Standby
Sleep
5279 tbl 13
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=V
DD
)
Sequence 1
A1
First Address
Second Address
Third Address
Fourth Address
(1)
0
0
1
1
A0
0
1
0
1
Sequence 2
A1
0
0
1
1
A0
1
0
1
0
Sequence 3
A1
1
1
0
0
A0
0
1
0
1
Sequence 4
A1
1
1
0
0
A0
1
0
1
0
5279 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=V
SS
)
Sequence 1
A1
First Address
Second Address
Third Address
Fourth Address
(1)
0
0
1
1
A0
0
1
0
1
Sequence 2
A1
0
1
1
0
A0
1
0
1
0
Sequence 3
A1
1
1
0
0
A0
0
1
0
1
Sequence 4
A1
1
0
0
1
A0
1
0
1
0
5279 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
