IDT71V3576S133PF 参数 Datasheet PDF下载

t

CYC

CLK

t

CH

t

CL

t

SS

t

HS

ADSP

(1)

ADSC

t

HA

Ax

t

SW

t

HW

Ay

t

SA

ADDRESS

GW,BWE,BWx

t

HC

t

SAV

t

HAV

t

SC

CE, CS

1

(Note 3)

Timing Waveform of Pipelined Read Cycle

(1,2)

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

6.42

13

t

OE

t

CD

t

OHZ

t

CDC

O1(Ay)

O2(Ay)

O3(Ay)

ADV

ADV

HIGH suspends

burst

OE

t

OLZ

t

CLZ

O1(Ax)

(Burst wraps around

to its initial state)

t

CHZ

O4(Ay)

O1(Ay)

O2(Ay)

DATA

OUT

Output

Disabled

Pipelined

Read

Burst Pipelined Read

5279 drw 08

NOTES:

1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence

of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the

LBO

input.

2. ZZ input is LOW and

LBO

is Don't Care for this cycle.

3. CS

0

timing transitions are identical but inverted to the

CE

and

CS

1

signals. For example, when

CE

and

CS

1

are LOW on this waveform, CS

0

is HIGH.

,