IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS
:
Data In (D
0
- D
8
) —
Data inputs for 9-bit wide data.
CONTROLS:
Reset (
RS
)
— Reset is accomplished whenever the Reset
(
RS
) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (
FF
) and Programmable Almost-Full Flag
(
PAF
) will be reset to HIGH after t
RSF
. The Empty Flag (
EF
) and
Programmable Almost-Empty Flag (
PAE
) will be reset to LOW
after t
RSF
. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK)
— A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (
FF
) and
Programmable Almost-Full Flag (
PAF
) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (
WEN1
)
— If the FIFO is configured for
programmable flags, Write Enable 1 (
WEN1
) is the only
enable control pin. In this configuration, when Write Enable 1
(
WEN1
) is low, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (
WEN1
) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (
FF
) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
FF
) will go HIGH after t
WFF
,
allowing a valid write to begin. Write Enable 1 (
WEN1
) is
ignored when the FIFO is full.
Read Clock (RCLK)
— Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (
EF
) and Programmable Almost-Empty Flag (
PAE
)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
Read Enables (
REN1
,
REN2
)
— When both Read Enables
(
REN1
,
REN2
) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
When either Read Enable (
REN1
,
REN2
) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (
EF
) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (
EF
) will go HIGH after t
REF
and a valid read can begin.
The Read Enables (
REN1
,
REN2
) are ignored when the FIFO
is empty.
Output Enable (
OE
)
— When Output Enable (
OE
) is
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (
OE
) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
Write Enable 2/Load (WEN2/
LD
)
— This is a dual-
purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which
allows depth expansion. If Write Enable 2/Load (WEN2/
LD
)
is set high at Reset (
RS
= LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (
WEN1
) is LOW and Write Enable 2/Load (WEN2/
LD
) is HIGH, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable (
WEN1
) is HIGH
and/or Write Enable 2/Load (WEN2/
LD
) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (
FF
) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
FF
) will go HIGH after t
WFF
,
allowing a valid write to begin. Write Enable 1 (
WEN1
) and Write
Enable 2/Load (WEN2/
LD
) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/
LD
) is set LOW at Reset
(
RS
=low). The IDT72421/72201/72211/72221/72231/72241
devices contain four 8-bit offset registers which can be loaded
with data on the inputs, or read on the outputs. See Figure 3
for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (
WEN1
) and Write Enable 2/Load (WEN2/
LD
) are set low, data on the inputs D is written into the Empty
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
5.07
6
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