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IDT72221L15J 参数 Datasheet PDF下载

IDT72221L15J图片预览
型号: IDT72221L15J
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS SyncFIFO 64 ×9 , 256 ×9 , 512× 9 , 1024 X 9 , 2048 ×9和4096 ×9 [CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9]
分类和应用: 先进先出芯片
文件页数/大小: 19 页 / 200 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the Write Enable 2/Load (WEN2/
LD
) pin HIGH, the
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/
LD
) pin is set LOW, and Write
Enable 1 (
WEN1
) is LOW, the next offset register in sequence
is written.
The contents of the offset registers can be read on the
output lines when the Write Enable 2/Load (WEN2/
LD
) pin is
set low and both Read Enables (
REN1
,
REN2
) are set LOW.
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
A read and write should not be performed simultaneously
to the offset registers.
LD
0
WEN1
0
WCLK
(1)
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
0
1
1
1
0
1
NOTE:
2655 drw 04
1. The same selection sequence applies to reading from the registers.
REN1
and
REN2
are enabled and read is performed on the LOW-to-HIGH
transition of RCLK.
Figure 2. Write Offset Register
8
72421 - 64 x 9-BIT
6 5
0
Empty Offset (LSB) Reg.
Default Value 007H
72201 - 256 x 9-BIT
8
7
Empty Offset (LSB) Reg.
Default Value 007H
0
8
7
72211 - 512 x 9-BIT
0
Empty Offset (LSB)
Default Value 007H
0
8
1
(MSB)
0
0
8
0
8
8
6 5
Full Offset (LSB) Reg.
Default Value 007H
0
8
7
Full Offset (LSB) Reg.
Default Value 007H
0
8
7
Full Offset (LSB)
Default Value 007H
0
8
0
8
0
8
1
(MSB)
0
0
72221 - 1024 x 9-BIT
8
7
Empty Offset (LSB) Reg.
Default Value 007H
8
1
(MSB)
00
8
7
Full Offset (LSB) Reg.
Default Value 007H
8
1
(MSB)
00
0
8
0
8
7
0
8
0
8
7
72231 - 2048 x 9-BIT
0
Empty Offset (LSB) Reg.
Default Value 007H
2
(MSB)
000
0
Full Offset (LSB) Reg.
Default Value 007H
2
(MSB)
000
Figure 3. Offset Register Location and Default Values
72241 - 4096 x 9-BIT
8
7
Empty Offset (LSB)
Default Value 007H
0
8
3
(MSB)
0000
8
7
Full Offset (LSB)
Default Value 007H
0
8
3
(MSB)
0000
0
0
0
0
2655 drw 05
5.07
7