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IDT72221L15J 参数 Datasheet PDF下载

IDT72221L15J图片预览
型号: IDT72221L15J
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS SyncFIFO 64 ×9 , 256 ×9 , 512× 9 , 1024 X 9 , 2048 ×9和4096 ×9 [CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9]
分类和应用: 先进先出芯片
文件页数/大小: 19 页 / 200 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
RS
RS
t
RSS
t
RSR
REN1,
REN2
t
RSS
t
RSR
WEN1
t
RSS
WEN2/
LD
(1)
t
RSR
t
RSF
EF
,
PAE
t
RSF
FF
,
PAF
t
RSF
Q
0
- Q
8
OE
= 1
OE
= 0
(2)
2655 drw 06
NOTES:
1. Holding WEN2/
LD
HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/
LD
LOW during reset will make the pin act as
a load enable for the programmable flag offset registers.
2. After reset, the outputs will be LOW if
OE
= 0 and tri-state if
OE
= 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
5.07
9