IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENH
tENS
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
t
REF
t
REF
EFA (EFB)
tA
QA
0
0
- QA
8
VALID DATA
(QB
- QB8)
tOLZ
tOHZ
tOE
OEA (OEB)
(1)
SKEW1
t
WCLKA, WCLKB
WENA1 (WENB1)
WENA2 (WENB2)
4093 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
Figure 6. Read Cycle Timing
WCLKA
(WCLKB)
tDS
DA
0
- DA
8
D1
D2
D3
(DB
0
- DB8)
tENS
D0 (First Valid
WENA1
(WENB1)
tENS
WENA2 (WENB2)
(If Applicable)
(1)
tFRL
tSKEW1
RCLKA
(RCLKB)
t
REF
EFA (EFB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
tA
QA
0
- QA
8
D0
D1
(QB
0
- QB8)
tOLZ
tOE
OEA (OEB)
4093 drw 09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
