IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
NO WRITE
NO WRITE
NO WRITE
WCLKA
(WCLKB)
tSKEW1
tSKEW1
tDS
tDH
DA
0
- DA
8
(DB0
- DB8)
t
WFF
tWFF
t
WFF
FFA (FFB)
(1)
ENS
t
t
ENS
ENS
t
ENH
WENA1
(WENB1)
(1)
ENS
t
t
ENH
t
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
tENH
tENH
tENS
tENS
RENA1
(RENB2)
tA
LOW
OEA
(OEB)
tA
QA
0
- QA
8
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB8)
4093 drw 10
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA
0
- DA
8
DATA WRITE 1
DATA WRITE 2
(DB
0
- DB8)
tENS
tENH
tENS
tENH
WENA1, (WENB1)
tENS
tENS
tENH
tENH
WENA2 (WENB2)
(If Applicable)
(1)
FRL
(1)
FRL
t
t
tSKEW1
tSKEW1
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
LOW
OEA (OEB)
tA
QA
0
- QA
8
DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB8)
4093 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
