IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tCLKH
tCLKL
(4)
WCLKA
(WCLKB)
tENH
tENS
WENA1
(WENB1
tENS
tENH
WENA2
(WENB2)
(If Applicable)
t
PAF
Full - (m+1) words in FIFO (1)
(2)
PAFA
(PAFB)
Full - m words in FIFO
(3)
tSKEW2
t
PAF
RCLKA
(RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
4093 drw 12
NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841,
or (8,192-m) words for the IDT72V851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB)
rising edge.
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLKA
(WCLKB)
tENH
tENS
WENA1
(WENB1)
tENS
tENH
WENA2
(WENB2)
(If Applicable)
n words in FIFO(1)
PAEA,
PAEB
n+1 words in FIFO
(2)
tSKEW2
t
PAE
t
PAE
(3)
RCLKA
(RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
4093 drw 13
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between
the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB)
rising edge.
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
12
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
