Functional Description
channel) or by the ISAC-S itself (transmission of an HDLC frame). A software access request
to the bus is effected by setting the BAC bit (CIX0 register) to "1".
In the case of an access request, the ISAC-S checks the Bus Accessed-bit (bit 5 of IDP1 last
octet of Ch2, see figure 39) for the status "bus free", which is indicated by a logical "1". If the
bus is free, the ISAC-S transmits its individual TIC bus address programmed in the STCR
register. The TIC bus is occupied by the device which sends its address error-free. If more than
one device attempt to seize the bus simultaneously, the one with the lowest address values
wins.
MR
MX
MR
MX
TAD
BAC
B1
B2
MON0 D CI0
IC1
IC2
MON1 CI1
BAC
TAD
1
ITD02575
2
0
TIC-Bus Address (TAD 2-0)
Bus Accessed (’1’ no TIC-Bus Access)
Figure 39
Structure of Last Octet of Ch2 on IDP1 (DU)
When the TIC bus is seized by the ISAC-S, the bus is identified to other devices as occupied
via the IDP1 Ch2 Bus Accessed-bit state "0" until the access request is withdrawn. After a
successful bus access, the ISAC-S is automatically set into a lower priority class, that is, a new
bus access cannot be performed until the status "bus free" is indicated in two successive
frames.
If none of the devices connected to the IOM interface request access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will therefore
have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the µP when access to the C/I channels is
no more requested, to grant other devices access to the D and C/I channels.
The availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the IDP0
last octet of Ch2 channel (figure 40).
S/G = 1 : stop
S/G = 0 : go
Semiconductor Group
77
INFINEON [ Infineon ]
